In this manner, the operation of an SOA- 2. These switching energy values are based switch can be discriminated in two regions, as shown indeed low, and the gate may operate in a loss-optimized logic in Fig. AMR for different CW gain values. In contrast, region B tems . It is particularly necessary in the design and develop- is narrower, corresponds to the heavy saturation regime of the ment of high-functionality multigate systems, as it is the way to SOA, and offers enhanced amplitude modulation suppression at synchronize the optical signals between remote processing units the output of the all-optical gate.
This pulse train was modulated with a electronic phase-locked loops , and self-pulsating DFBs pseudorandom binary sequence PRBS signal from a , . Ring lasers and phase-locked loops require a long pattern generator and a LiNbO modulator MOD1 and was time for synchronization to the data streams and are not suitable three-times bit-interleaved to generate a Self-pulsating data stream. Data packets of variable length and period were DFBs require significantly less overhead for clock acquisition formed using a second modulator MOD2 driven from a pro- and have been demonstrated to operate successfully with asyn- grammable pulse generator.
The packet stream was amplified in chronous data packets comprising of a few thousands of bits EDFA1 and split into two different optical paths via a 3-dB fiber and guard bands of a few hundreds of bits , at rates up to coupler. Here, we describe an all-optical clock-recovery of Packet clock-recovery experimental setup.
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Variable ODLs ODL1 and ODL2 were also used to independently con- trol the relative arrival time of the packets at the clock-recovery circuit so as to investigate the minimum acceptable delay be- tween successive packets and to assess the circuit ability to op- erate with successive packets that are asynchronous at the bit level.
The active el- ement was a 1. After exiting the SOA, the polarization components of the CW signal were filtered in a 2-nm filter, had their relative delay removed, and were made to interfere in PBS2. The interferometer was biased so that, in the absence of the control signal, the CW signal appeared at its unswitched port U, while in the presence of the control, it ap- Fig. Packets typical data stream, obtained from the asynchronous packet flow 2 and 3 are shown in more detail in Fig. More specifically, a sequence of four data packets is tively.
Packets 1 and 3 are traveling through the upper, and the exponentially decaying response function of the filter so that packets 2 and 4 are traveling through the lower branch of the an amplitude modulated, but clock ressembling signal is ob- packet generator. The coarse relative delay between packets 1 tained. This amplitude ratio varies between a maximum value and zero, depending on whether the packets are perfectly phase-aligned or misaligned by , and this adjustment is provided by the setting of ODL1 or ODL2 within a bit-period time interval of approximately ps.
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This formed the technological platform for the development of an Fig. The optical LFSR is c and d corresponding recovered packet clocks. This is used as the control signal into the ceiver of the BERT. Moreover, regenerative optical memories UNI gate to induce an almost -phase shift between the orthog- are useful network units because they can store data packets onal polarization components of the CW signal. The first short rise and fall times.
A more detailed representation of the recovered switches , , but they were not suitable for single-packet packet clocks for packets 2 and 3 is illustrated in Fig.
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On the other hand, regenerative buffers using The packet clocks display rise and fall times of 2 and 8 b, compact semiconductor interferometric switches are character- respectively, and amplitude modulation of less than 1. Packet clocks of the same quality were obtained irre- Fig. The UNI was also examined using a GHz microwave spectrum gate is utilized in a counterpropagating configuration and is analyzer.
The signal packet signal from dc to The pulsewidth of both signals was 9 ps after linear MHz-spaced packet subharmonics. For the memory loop or the shift register to be the corresponding output of the FPF. The effect of the filter realized, the S-port of the UNI gate is fed back into the gate as is primarily to suppress all data modes outside a MHz control signal.
Data are loaded up once at start-up and are let band around the baseline rate. Data-mode suppression within to perform several recirculations after which they exit the this MHz band is achieved by taking advantage of the memory circuit. In this manner, if the amount of time that data nonlinear transfer function of the deeply saturated SOA-based need to travel once the feedback loop is , then buffering times interferometric gate .
Finally, the root-mean-square rms timing jitter light in vacuum, it can be deduced that the primary factor that of the extracted clock was also calculated using the microwave affects the ultimate storage time is the length of the feedback spectrum analyzer for a total span of 3 KHz around the packet loop, which in turn is the sum of the physical length and the clock components and resolution bandwidth of 10 Hz and was pigtails of the active and passive components it consists of found to be less than 1 ps. This essentially means It should also be noted that the amplitude ratio between the that the storage time can be altered at will by simply adding Block diagram of an optical regenerative memory.
Electronic equivalent of a regenerative buffer. The this SOA-based interferometric type of memory. However, the active switching device in the UNI was the same SOA that introduced latency must be kept at the same time to acceptable was used in the switch configured as an AND gate, and each of values for ultra-high-speed all-optical applications, namely to the two PMFs was arranged to introduce ps relative delay the order of few tens of nanoseconds so that real-time data between the two orthogonal polarization clock components.
Thus, provided that the total width of the The length of the feedback circuit was The shift register recirculation time was ns. Variable bits and their period in the data sequence of each packet, as well delay lines were used for precise time synchronization between as the time delay guard band between them, is appropriately the three optical signals. In the absence of the control signal, adjusted so as to correspond to the single circulation time the output appears in the U-port of the UNI gate; otherwise, through the shift register, then it can be stored if its period it appears in the S-port.
It should be noted that if there is no satisfies for a certain. It must be noted that since circuit available to load up a data sequence, only the U-port this is a regenerative memory and pulses are replaced in each may be used to provide the feedback or else the memory will circulation without performance degradation, there is actually never start to operate.
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The two signals were monitored with an analogue os- cilloscope using two photodiodes and the chop vertical mode. It was also possible to monitor the stored pattern through more than 80 successive circulations, corresponding to more than 57 s of storage time, and the stored pattern still presented no deteriora- tion. The data circuit after 40 circulations upper row and the corresponding load-up signal frame consists of four data packets, while each data packet is lower row.
In this case, the frame consists of a ns ther signal processing for reading out the packets. On the other data packet, which contains The period of the load-up signal was ad- and have higher quality with respect to extinction ratio, com- justed to be 5.
Consequently, the performance of total storage time 5.
It is worth noting that the first the circuit at the bit level is expected to be better when the S-port harmonic of the recirculating signal, which occurs at 1. The pulse energies of the clock, loading-up, and recirculating signals were 3, 23, and 33 fJ, respectively, making this memory a low-energy-consumption circuit. Oscilloscope trace of a the load-up signal, b the memory content vice consisting of consecutive two-state memory units, which with the S-port of the UNI used in the feedback circuit, and c the memory content with the U-port of the UNI used in the feedback circuit.
All the memory units change state together in synchronization with the input clock pulses, and in every clock pulse the content of each memory unit is shifted to the next one. If no signal is introduced into the first delay element during this process, then at the end of shifts all the memory units will have no content. To convert the shift register from a delay line unit to a sequence generator, a feedback loop is needed.
The feedback loop feeds the content of certain memory units, which are called taps, into a modulus 2 adder XOR operation and then back to the first memory unit. Block diagram of an electrical LFSR.
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In that way, a new term is computed for the first stage based on some of the previous terms. In order for the circuit to start producing bi- th memory unit or -tap. The fused fiber coupler offering the advantage of speed. The optical shift registers, and with splitting ratio forms two optical loops with lengths the SOA-based interferometric XOR gates discussed so far can and so that the IC signal is split in two de- be used for the implementation of an all-optical LFSR.
How- layed replicas, which are launched as control signals into the ever, the huge size of the optical shift register restricts the ap- gate ports 1 and 2. Despite this fact, the loop so that the process can repeat itself. The longest optical a design algorithm has been constructed to allow for easy pro- path can be considered as the entire shift register or the first gramming of the all-optical LFSRs, irrespective of the shift reg- feedback, while the shortest one is the second feedback of the ister size.
In this configuration, two taps are selected: the last one Fig. The optical shift register is constructed implemented with the UNI. Block diagram of an all-optical LFSR.
Generic block diagram of BERT equipment. The design and demonstration of the all-op- nents and fiber, and is the repetition frequency of the clock tical BERT relies not only on the maturity of these modules but signal driving the circuit. It should be noted that the FFs of an on their functional integration as well.